Abstract: In certain embodiments, a method includes the following steps. An engineering change order (ECO) is for fixing a violation of a target constraint on a target netlist of an integrated circuit. A constraint on a related netlist of the integrated circuit is identified. The identified constraint is adversely affected by fixing the violation of the target constraint. A processor concurrently modifies the target netlist to fix the violation of the target constraint and modifies the related netlist to prevent violation of the adversely affected constraint.

Abstract: A system-in-package architecture in accordance with aspects includes a logic die and one or more memory dice coupled together in a three-dimensional slack. The logic die can include one or more global building blocks and a plurality of local building blocks. The number of local building blocks can be scalable. The local building blocks can include a plurality of engines and memory controllers. The memory controllers can be configured to directly couple one or more of the engines to the one or more memory dice. The number and type of local building blocks, and the number and types of engines and memory controllers can be scalable.

Abstract: Methods, systems, and devices for pin mapping for memory devices are described. An apparatus may include a memory array, a plurality of pins, a selector, and a mapping component. The memory array may include a plurality of data lines coupled with a plurality of memory cells. The mapping component may be configured to map a set of data lines to a first set of pins when the selector reflects a first state and to a second set of pins when the selector reflects a second state. The first and second set of pins may have a same quantity of pins. The second set of pins may include pins that are otherwise unused in the second state. The mapping component may be configured to selectively couple unused pins to a fixed potential.

Abstract: In accordance with various embodiments and aspects of the invention, systems and methods are disclosed that can automatically find the best legal configuration that will be optimal with respect to a given set of requirements or metrics, such as: area, timing, and power. A designer defines the metrics or requirements, which represent the functional needs. A designer typically selects a set of parameters from a group of parameters available to user, which are user selectable parameters. The best parameters, from which the user can select parameters, are identified, and provided to the user. A constraint solver module ensures all rules are enforced and finds all legal parameters that fulfil the user intent. The constraint solver module generates configurations that meet the requirements and are legal configurations.

Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Traffic data is determined or received, and a baseline topology is generated or received. For each router in the baseline topology, a number of edge virtual channel (EVC) combinations is determined, the transmittablility of the traffic classes are determined, and, when the traffic classes are not transmittable, the router is identified. A traffic class affinity graph (TCAG) is generated for each identified router. Traffic class combinations are generated for the identified routers based on the TCAGs and EVC combinations. The traffic classes of the identified routers are merged based on the traffic class combinations. A final EVC combination for each identified router is determined based on the merged traffic classes. A final topology is generated based, at least in part, on the merged traffic classes and the final EVC combinations for the identified routers.

Abstract: The present disclosure provides a computer-based method and system for synthesizing a Network-on-Chip (NoC). Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow to create a plurality of VC assignments. A topology is generated, based on the physical data, the device data, the bridge data, the traffic data and the VC assignments, which includes bridge ports, routers and connections. Final locations for relocatable NoC elements (e.g., routers, etc.) are determined based on NoC element energy values for the relocatable NoC elements, and protocol-level pipelines may be inserted into the connections based on a timing parameter.

Abstract: A computer implemented method is disclosed relating to the design of electronic circuits and systems. In some examples, a graphical user interface is utilized to receive first information relating to a requested electronic circuit. The first information includes a selected type of electronic circuit and one or more operating criteria relating to requested fundamental functionality of the selected type of electronic circuit. Second information is also received, relating to requested secondary attributes of a hypothetical candidate electronic circuit that satisfies the first information. In response, a set of candidate circuit architectures are displayed satisfying the first information, as well as a visualization of how each of the candidate circuit architectures relates to the second information.

Abstract: A design system is provided. In one embodiment the design system includes an input module to receive specification data for a designed circuit including a configurable integrated circuit (IC). The configurable IC includes a number of analog elements for which parameters can be set by the design system, and a plurality of configurable signal path elements including an analog-to-digital converter (ADC) that is utilized in a plurality of different signal paths. The design system further includes a design module to generate a design for the designed circuit based on the specification data, and an output module to set parameters of at least one of the analog elements based on the design. Other embodiments are also provided.

Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.

Abstract: One embodiment of the present invention provides a system that facilitates reducing static power consumption of a processor. During operation, the system receives a signal indicating that instruction execution within the processor is to be temporarily halted. In response to this signal, the system halts an instruction-processing portion of the processor, and reduces the voltage supplied to the instruction-processing portion of the processor. Full voltage is maintained to a remaining portion of the processor, so that the remaining portion of the processor can continue to operate while the instruction-processing portion of the processor is in reduced power mode.

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify a specification of an electronic design, a parameter for optimization, at least one optimization target for the parameter, and initial grids for the electronic design. An optimization map may be determined, by at one or more optimization modules that are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system, for the electronic design at least by performing one or more analyses that refine the initial grids for the optimization map with respect to the parameter and the at least one optimization target. The electronic design may be implemented based at least in part upon the optimization map.

Abstract: This application discloses a computing system to identify a stage of a logic pipeline described in a circuit design that, when implemented in configurable hardware, spans between partitions in the configurable hardware. The computing system can modify the circuit design to alter a timing for logic operations in the logic pipeline, which reduces slack in at least one stage in the logic pipeline adjacent to the identified stage in the logic pipeline. The computing system can utilize the slack reduced from at least one of the stages adjacent to the identified stage to increase a clock frequency in the configurable hardware or increase a time available for propagation delay associated with the identified stage. The computing system can generate a configuration for the configurable hardware that implements the logic pipeline with the altered timing in the configurable hardware.

Abstract: Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.

Abstract: A cryptographic ASIC and method for autonomously storing a unique internal identifier into a one-time programmable memory in isolation by a foundry. The identifier may be determined by calculating a transformed hash of a predetermined input, and may serve as a cryptographically defined and verifiable CpuID for a particular ASIC instance. The CpuID may be derived from an input based on a manufacture date, a wafer lot number, a wafer number, row and column coordinates for a die on a wafer, or other foundry-defined data. The CpuID enables a given ASIC instance to be securely and remotely identified across an untrusted network, and to serve as a specified processor that originates an information stream or a message. The ASIC need not always perform high-speed calculations and so may be relatively simple and inexpensive, and in one embodiment serves as a secure data administrator that manages subscriptions and software updates.

Abstract: Devices and methods for reconfiguring a programmable fabric include identifying resources in a programmable fabric of the programmable device as belonging to a partition. Reconfiguring the programmable fabric also includes creating a mask for the partition that indicates that the identified resources belong to the partition. Reconfiguring the partition also includes reconfiguring resources, via a configuration controller, in programmable fabric associated with the partition using the mask without changing resources associated with other partitions in the programmable fabric.

Abstract: In certain aspects of the disclosure, an apparatus includes first and second semaphore registers disposed in a first power domain. A common address bus is coupled to the first and second semaphore registers, and a semaphore lock is disposed in the first power domain and coupled to the first and second semaphore registers. The semaphore lock is controlled by the first and second semaphore registers, and controls whether a signal from a second power domain is permitted to propagate to the first power domain. The first and second semaphore registers may be associated with first and second register addresses, respectively, which are selected to provide a substantially maximized Hamming distance between them. The first and second semaphore registers may have a write order expectation enforced between them.

Abstract: Two retention flip-flop topologies that utilize a data retention control circuit and a slave/retention latch (sub-circuit) to reliably retain a data bit during standby/sleep operating modes without the need for a local clock signal. The slave/retention latch is controlled using a local clock signal to store sequentially received data bit values during normal operating modes. During standby/sleep modes, the local clock signal is de-activated (i.e., by turning off the supply voltage provided to the local clock generator circuit), and the data retention control circuit operates in accordance with an externally supplied retention enable control signal to both isolate and control the slave/retention latch such that a last-received data bit value is reliably retained in the slave/retention latch. When normal operation is resumed, the local clock signal is re-activated, and the data retention control circuit controls the slave/retention latch to pass the last-received data bit value to an output driver.

Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.

Abstract: A design system is provided. In one embodiment the design system includes an input module to receive specification data for a designed circuit including a configurable integrated circuit (IC). The configurable IC includes a number of analog elements for which parameters can be set by the design system, and a plurality of configurable signal path elements including an analog-to-digital converter (ADC) that is utilized in a plurality of different signal paths. The design system further includes a design module to generate a design for the designed circuit based on the specification data, and an output module to set parameters of at least one of the analog elements based on the design. Other embodiments are also provided.

Abstract: An information processing apparatus includes a control unit configured to activate the information processing apparatus in a first activation mode or a second activation mode, a receiving unit configured to receive an operation for activating the information processing apparatus in the first activation mode from a user, a notification unit configured to notify the control unit of information corresponding to the operation of the user received by the receiving unit, and a connection unit configured to connect the control unit and the receiving unit without connecting the notification unit and to notify the control unit that a user has operated on the receiving unit, wherein the control unit activates, in the case where it is not notified via the connection unit that a user has operated on the receiving unit, the information processing apparatus in the second activation mode without waiting for activation of the notification unit.

Abstract: An information processing apparatus includes a control unit configured to activate the information processing apparatus in a first activation mode or a second activation mode, a receiving unit configured to receive an operation for activating the information processing apparatus in the first activation mode from a user, a notification unit configured to notify the control unit of information corresponding to the operation of the user received by the receiving unit, and a connection unit configured to connect the control unit and the receiving unit without connecting the notification unit and to notify the control unit that a user has operated on the receiving unit, wherein the control unit activates, in the case where it is not notified via the connection unit that a user has operated on the receiving unit, the information processing apparatus in the second activation mode without waiting for activation of the notification unit.

Abstract: A system and method that tests an IP component of a hardware design generates an abstract model of the IP component based on knowledge of the design and one or more protocols implemented with the IP component. A generic driver and associated interfaces are additionally generated or selected to test the IP component within the hardware design.

Abstract: Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design.

Abstract: Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.

Abstract: An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.

Abstract: A system for prototyping an integrated circuit (IC) that has a mixed signal intellectual property (IP) core includes implementing the IP core using discrete programmable digital ICs and discrete analog ICs by partitioning the IP core into a digital IP portion and an analog IP portion.

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Abstract: A hierarchical interface module includes an assessment unit configured to identify a hierarchical implementation incompatibility of an integrated circuit (IC) partitioned block. Additionally, the hierarchical interface module includes an interface unit configured to substitute a directly registered hierarchical interface structure for the hierarchical implementation incompatibility of the IC partitioned block. A method of interfacing hierarchically and a hierarchical implementation system are also included.

Abstract: An imaging solution that uses a small, adaptable, real-time, scalable, image-processing (SMARTS IP) chip configured to function like any one of a wide range of specialized FPA imaging devices, and a method for configuring and implementing same is provided. Configuration for a wide range of applications and implementations, including ones with or without IDCA assemblies or other types of dewar/cooler structures, is disclosed. A wide range of output data formats, including all SDI-compatible image data formats, may be accomplished. Frame stacking and variable effective resolution and charge well depth levels may be accomplished in output image data based on on-chip image processing techniques. On-chip image processing algorithms may include XR™, DRC, NUC, and other similar or related techniques. Image data output compression through on-chip processing is also disclosed.

Abstract: There is provided a mechanism of preferentially using a memory layer which suffers a small influence of heat of an SOC die, based on the positional relationship between the SOC die and the memory layer, and decreasing the refresh frequency of the DRAM and a leakage current. To accomplish this, an information processing apparatus allocates, in order to execute an accepted job, a memory area for executing the job preferentially from a memory physically farthest from the SOC die among a plurality of memories, and then executes the job.

Abstract: An Infrastructure Description Language (IDL) includes Service Level Hints (SLHs) and Service Level Requirements (SLRs). The SLHs and SLRs are used to configure at least one hardware resource in a computing system having an intelligent configurator to broker a hardware configuration based on the SLHs and SLRs.

Abstract: Various embodiments of the present disclosure provide techniques for producing configuration images of a system on a chip (SOC) design, including a programmable logic device (PLD) and operating system (OS) packages, responsive to a user selection of one or more modules of the PLD and a user selection of at least one OS package. A processor configured to run a design tool, builds the configuration image of the SOC. The design tool compiles a PLD configuration image corresponding to the first selection, selects one or more PLD module drivers corresponding to the first selection, compiles a bootloader and OS kernel design corresponding to the selected one or more module drivers and the PLD image; and builds the configuration image of the SOC corresponding to the bootloader and OS kernel design and the second selection.

Abstract: A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.

Abstract: The present patent document relates to a method and apparatus for an automatic clock to enable conversion for FPGA-based prototyping systems. A library or netlist is provided having a plurality of state elements of a chip design to be prototyped by a user. The chip design can have dozens of different user clocks and clock islands using these different user clocks. The state elements of an element library or netlist are converted to a circuit having one or more state elements and other logic that receive both a user clock as well as a fast global clock. With the disclosed transformations, the functionality of the original state element is maintained, and a single or low number of global clocks can be distributed in an FPGA of the prototype with user clocks generated locally on the FPGA.

Abstract: Methods, systems, and computer readable medium for developing a system architecture that involves defining resource constraints for kinds of resources and constraint values for optimization parameters, and defining a design space as variants, where each variant is a vector. Satisfying sets of variants are determined for optimization parameters by assigning membership values to each variant of a universe of discourse set and performing a fuzzy search of a universe of discourse set using the corresponding membership values. A set of variants is determined based on an intersection of the satisfying sets of variants. An ordered list of variants is generated by sorting the set of variants and a variant is selected based on a position of the variant in the ordered list for use in developing the system architecture.

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Abstract: A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

Abstract: Example implementations described herein are directed to a system on chip (SoC) that can include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality of routers, and a plurality of links between routers. The plurality of blocks and the plurality of routers are interconnected by the plurality of links using a Network-on-Chip (NoC) architecture with a sparse mesh topology. The sparse mesh topology involves a sparsely populated mesh which is a subset of a full mesh having one or more of the plurality of routers or links removed. The plurality of blocks communicate among each other by routing messages over the remaining ones of the plurality of routers and links of the sparse mesh.

Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.

Abstract: A method includes retrieving a first component information of a secured portion of a package, wherein the first component information is encrypted. The step of retrieving includes decrypting the first component information. A thermal resistance-network (R-network) is generated from the decrypted first component information. A temperature map of the package is generated using the thermal R-network and a second component information of an unsecured portion of the package, wherein the secured portion and the unsecured portion are bonded to each other.

Abstract: A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.

Abstract: In one embodiment, a method is provided for processing a circuit design having first and second sets of ports configured to couple to respective first and second sets of ports of a device on a hardware platform. In a data-acquisition mode, the circuit design is simulated using a user-selectable plug-in that couples the ports of the circuit design to an interface circuit. During the simulation, the interface circuit communicates data between respective ports of the circuit design and ports of the device. In a deployment mode, the circuit design is implemented in the hardware platform, in which the first and second sets of ports of the circuit design are respectively coupled to the first and second sets of ports of the device.

Abstract: A user interface for a computer-aided design tool includes a display. The display includes a visualization of a processor system of a system-on-a-chip (SOC). The visualization includes a plurality of blocks and each block represents a component of the processor system. Each block visually indicates a configuration status of the component represented by the block.

Abstract: Designing operation efficiency is improved by automatically transmitting and receiving circuit-related information and layout-related information required for designing each printed board between printed boards, for designing a plurality of printed boards at the same time. In an electric information processing method in a CAD system, the printed boards are designed at the same time by transmitting and receiving the circuit design information relating to the printed boards and the layout design information relating to the printed boards between the circuits and layouts relating to the printed boards.

Abstract: According to an embodiment, a semiconductor integrated circuit including first and second lower-layer power supply wires extending in a first direction and first and second upper-layer power supply wires extending in a second direction is provided. First and second connection wires between the upper-layer power supply wires and the lower-layer power supply wires are arranged in a same line along the second direction. First and second position converting wires extending from the connection wires are arranged between the first and second connection wires. First and second upper-side vias provided on the position converting wires are arranged in a same line along the first direction.

Abstract: In various embodiments, an integrated circuit layout is disclosed. In one embodiments, the integrated circuit layout comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non-opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area.

Abstract: A present ASIC may include functionality exceeding that which will be operative at one given time (e.g., when the chip is packaged and inserted into a broader circuit). The excess ASIC functionality may be chosen in anticipation of changing market environments, and/or differing product requirements in various market spaces (e.g., in different countries where different interoperability standards are chosen). In such cases, an appropriate subset of the excessive ASIC functionality may be programmably activated for each market space after manufacture.

Abstract: A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.